An Efficient Systolic Architecture for All-One Polynomials Multiplier
نویسنده
چکیده
This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. The field-programmable gate array synthesis results shows that the proposed design provides significantly less area-delay complexities over the best of the existing designs.
منابع مشابه
GF(2) Based Polynomials Multiplier Using An Efficient Systolic Multiplier
This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input ...
متن کاملLow-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach
Recently, the multipliers with subquadratic space complexity for trinomials and some specific pentanomials have been proposed. For such kind of multipliers, alternatively, we use double basis multiplication which combines the polynomial basis and the modified polynomial basis to develop a new efficient digit-serial systolic multiplier. The proposed multiplier depends on trinomials and almost eq...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. 
The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...
متن کاملBit-Level Systolic Architecture for a Matrix-Matrix Multiplier
Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial parallel multiplier, which can perform both positive and n...
متن کامل